Monthly Archives: May 2013

For my current project, a backplane bus, I need to distribute a shared clock signal to all participants on the bus. I don’t want to impose any rules on the topology of the bus and the number of participants and bus length (as in length of the wires) is variable. This means that I have to assume that there will be quite a few reflections. This is no problem for the data lines as they will only be read out once they have stabilised, but the signal to read or write is transmitted as a clock and reflections there can be messy.

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Today I would like to present a little tutorial how to program a CPLD (in this case a Xilinx XC9572XL) using Ubuntu 12.4 LTS (64 bit) and the Bus Pirate v3. All the information needed to achieve this is already out there, but not conveniently boiled down to a tutorial. At least I did not find one. So here we go:

The first thing you will need to program Xilinx CPLDs, is Xilinx’s ISE development environment. Fortunately there is a version for Linux, but unfortunately it took a few tricks to make it work on my system. I cannot guarantee that any of this will be necessary or even advisable for you since it might depend on your flavour of Linux and version of ISE, but it worked for me.

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