Distributing a clock signal on a bus with strong reflections using Gray code

For my current project, a backplane bus, I need to distribute a shared clock signal to all participants on the bus. I don’t want to impose any rules on the topology of the bus and the number of participants and bus length (as in length of the wires) is variable. This means that I have to assume that there will be quite a few reflections. This is no problem for the data lines as they will only be read out once they have stabilised, but the signal to read or write is transmitted as a clock and reflections there can be messy.

To get around this problem, I decided to transmit my clock not on 1 but on 4 wires using Gray code. Gray code is another way of representing numbers in binary, where the difference between two consecutive numbers is always just one bit flip. So if you are counting in Gray code, each count only changes one bit in your number.

If we interpret each count of the Gray number as a clock edge, and only accept increasing numbers, we can ignore the reflections on the bus. To be more precise: We only accept a change in the Gray number if it is the next in line. So if a reflection causes the number to briefly switch back to its previous value, we just ignore it.

As a schematic this idea looks like this:

gray_clk_schem

The 4xFlipFlop FD4 holds the current Gray number. The gray2bin, inc, bin2gray chain computes the next Gray number, which differs from the current one by just one bit. The comparator checks if the Gray number at the pins match the next number and if so, clocks the next number into the FlipFlops so it becomes the current number. Even if, due to reflections, the number at the pins temporarily changes back to the previous number, nothing happens as the comparator will only react to the (now incremented) next number in line. I simulated a clock with strong reflections and it looks like the concept would work as intended:

gray_clk_signal

The signal BIN_CNT represents the current clock cycle in standard binary format. The lowest bit will flip on every update of the current number and thus can be used as a clock. The other bits can be used as a counter which I will also need for my bus design. If you do not need a counter, the minimal number of wires needed for this clock distribution scheme is 2. Since you are only transmitting one bit of information, you technically waste one bit of bandwidth, but you can safely ignore any reflections, as long as they subside till the next clock edge.

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